1. Technical Field
The present disclosure relates to an imaging device and more particularly to an imaging device that has a photoelectric conversion unit which includes a photoelectric conversion film and is laminated on a semiconductor substrate.
2. Description of the Related Art
A laminated type imaging device has been suggested as a metal oxide semiconductor (MOS) type imaging device. In the laminated type imaging device, a photoelectric conversion unit is laminated on the outermost surface of a semiconductor substrate, and charge generated through photoelectric conversion in the photoelectric conversion film is stored in a charge storage region (also referred to as “floating diffusion region”). The imaging device uses a charge coupled device (CCD) circuit or a complementary MOS (CMOS) circuit in the semiconductor substrate to read out the stored charge. For example, International Publication No. 2014/002367 discloses such an imaging device.
There has been a desire for noise reduction in the field of imaging devices. Particularly, it is desired that kTC noise (also referred to as “reset noise”) that occurs at resetting be reduced. As illustrated in FIG. 1, above International Publication No. 2014/002367 discloses an imaging device that is provided with a feedback circuit which negatively feeds back output of an amplifier transistor (21) in a unit pixel cell (20). International Publication No. 2014/002367 suggests reduction in the influence of kTC noise by forming the feedback circuit at a reset time of a charge storage node (25) (paragraph [0033]).
In the imaging device disclosed in International Publication No. 2014/002367, power supply wiring (27) is arranged between a feedback signal line (30) and metal wiring (40) in the same layer as the feedback signal line (30), among the feedback signal line (30) that is connected with an output terminal of a feedback amplifier (31) and the charge storage node (25). This reduces the coupling capacitance between the feedback signal line (30) and the metal wiring (40). The disclosure of International Publication No. 2014/002367 will be incorporated by reference herein in its entirety.
Japanese Patent No. 3793202 discloses that plural shield layers connected together by a pin are arranged between output lines. Japanese Patent No. 3793202 also discloses that such a configuration enables crosstalk between mutually adjacent output lines to be reduced.